1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a fabricating method of a liquid crystal display for substantially eliminating a process byproduct remaining within a chamber.
2. Description of the Related Art
Generally, liquid crystal displays controls the light transmittance of liquid crystals using an electric field to display a picture. To this end, the liquid crystal display includes a liquid crystal display panel with liquid crystal cells arranged in a matrix, and a drive circuit to drive the liquid crystal display panel. Pixel electrodes and common electrodes are provided to apply an electric field across each of the liquid crystal cells in the liquid crystal display panel. Normally, a pixel electrode is formed on a lower substrate of the liquid crystal cells, whereas the common electrode is integrated into the entire surface of an upper substrate. Each pixel electrode is connected to a thin film transistor (hereinafter, referred to as TFT) that is used as a switching device. The pixel electrode drives the liquid crystal cell together with the common electrode in accordance with data signals applied through the thin film transistor.
The lower substrate of such a liquid crystal display requires a plurality of mask processes as well as semiconductor processings. Thus, the fabricating process is complicated and a major factor in the cost of the liquid crystal display panel. This is because one mask process is used for several processes, such as a deposition process, a cleaning process, a photolithography process, an etching process, an exfoliation process and a testing process. To address this cost issue, a fabrication process for the lower substrate has been developed to reduce the number of mask processes. Accordingly, a four-mask process is now used for what was once a five-mask process.
FIGS. 1 and 2 are plan and sectional views representing a lower substrate formed by a four-mask process. Referring to FIGS. 1 and 2, a lower substrate 1 of a liquid crystal display includes a TFT T located adjacent each intersection of the data lines 4 and the gate lines 2, and a pixel electrode 22 connected to the drain electrode 10 of the TFT T. The TFT T includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected to the pixel electrode 22 through a drain contact hole 20. Further, the TFT T includes semiconductor layers 14 and 16 that form a conductive channel between the source electrode 8 and the drain electrode 10 when a gate voltage is applied to the gate electrode 6. In response to a gate signal from the gate line 2, the TFT T supplies a data signal from the data line 4 to the pixel electrode 22.
The pixel electrode 22 is located in a cell area defined by the data line 4 and the gate line 2 and formed of a transparent conductive material with high light transmittance. The pixel electrode 22 is formed on a protective layer 18 that is spread over the entire surface of the lower substrate 1, and is electrically connected to the drain electrode 10 through a drain contact hole 20 that penetrates the protective layer 18. A potential difference is generated between the pixel electrode 22 and a common transparent electrode (not shown) formed in an upper substrate (not shown) by the data signal supplied through the TFT T. The potential difference causes the liquid crystals located between the lower substrate 1 and the upper substrate (not shown) to rotate due to dielectric constant anisotropy. The rotating liquid crystals cause light incident through the pixel electrode 22 from a light source to be transmitted to the upper substrate.
The fabricating method of the lower substrate of the liquid crystal display will be described in conjunction with FIGS. 3A to 3D. FIGS. 3A to 3D are a sectional view representing processing steps for a lower substrate of the liquid crystal display shown in FIG. 2. As shown in FIG. 3A, a gate pattern, including the gate electrode 6 and the gate line 2, is formed on the lower substrate 1. To this end, a gate metal layer is deposited on the lower substrate 1 by a deposition method, such as sputtering. The gate metal layer is formed of aluminum Al or aluminum alloy. The gate metal layer is patterned by a photolithography and etching process using a first mask to form a gate electrode 6 and the gate line 2 on the lower substrate 1.
Referring to FIG. 3B, a gate insulating film 12, an active layer 14, an ohmic contact layer 16, a data line 4, a source electrode 8 and a drain electrode 10 are formed on the lower substrate provided with the gate electrode 6 and the gate line 2. The gate insulating film 12, first and second semiconductor layers and a data metal layer are sequentially deposited on the lower substrate 1 by a deposition method, such as chemical vapor deposition or sputtering. The gate insulating film 12 is formed of an inorganic insulating material, such as silicon oxide SiOx or silicon nitride SiNx. A first semiconductor layer is formed of undoped amorphous silicon doped with no impurities. A second semiconductor layer is formed of amorphous silicon doped with n-type or p-type impurities. The data metal layer is formed of molybdenum Mo or molybdenum alloy.
A photo resist pattern is formed on the data metal layer by a photolithography process using a second mask. In this case, a diffractive mask with a diffracting part at a channel part of the TFT is used as the second mask. Thus, the photo resist pattern of the second mask for the channel part is relatively lower in height than a source and drain pattern part. The data metal layer is patterned by a wet etching process using photo resist pattern of the second mask, whereby a data pattern including the data line 4, the source electrode 8 and the drain electrode 10 is formed.
Then, the first and second semiconductors are patterned by a dry etching process using the photo resist pattern of the second mask to form an active layer 14 and an ohmic contact layer 16. The photo resist pattern of the second mask with a relatively low height at the channel is removed by an ashing process, and then the data metal layer at the channel part is etched by a wet etching process and the ohmic contact layer is etched by the dry etching process. Accordingly, the active layer 14 of the channel part is exposed to separate the source electrode 8 from the drain electrode 10. Then, the remaining photo resist pattern is removed from the data metal layer by a stripping process.
Referring to FIG. 3C, a protective film 18 is formed on the gate insulating film 12 where the data pattern is formed. To this end, an insulating material is deposited on the gate insulating film 12 to form the protective film 18. The protective film 18 is formed of an inorganic insulating material, such as silicon nitride SiNx and silicon oxide SiOx, or an organic insulating material, such as acrylic organic compound, benzocyclobutene BCB, and perfluorocyclobutane PFCB. Subsequently, the protective film 18 is patterned by the photolithography process and the etching process using a third mask to form the drain contact hole 20. The drain contact hole 20 is formed to penetrate the protective film 18 and to expose the drain electrode 10.
As shown in FIG. 3D, the pixel electrode 22 is formed on the protective film 18. To this end, a transparent metal layer is formed on the protective film 18 by a deposition method such as sputtering. The transparent metal layer is formed of indium-tin-oxide ITO, indium-zinc-oxide IZO or indium-tin-zinc-oxide ITZO. Subsequently, the transparent metal layer is patterned by a photolithography and etching process using the fourth mask to form the pixel electrode 22. The pixel electrode 22 is connected to the drain electrode 10 through the drain contact hole 20 that penetrates the protective film 18. Contact holes formed on the gate pattern and the protective layer of the related art liquid crystal display are patterned by the dry etching process, and the semiconductor layer forming the channel between the source and drain electrodes is patterned by the ashing process and the dry etching process.
After the dry etching process and the ashing process, a method of eliminating a process byproduct, as shown in FIG. 4, is performed in order to remove the process byproduct remaining within the chamber. FIG. 4 is a flow chart representing a process to eliminate a process byproduct generated during a dry etching process and an ashing process of the liquid crystal display according to the related art.
First, as referred to in FIG. 4, after inserting a first substrate where the gate metal layer Mo or the protective film is formed into the chamber, the contact hole penetrating the gate pattern or the protective film is formed on the first substrate (step S41). The first substrate is removed from the chamber after completion of the dry etching process. After inserting a dummy substrate into the chamber, the photo resist and Molybdenum Mo remaining with the chamber are removed using SF6 gas and O2 gas with RF power (step 2 S42). At this moment, SF6 gas to O2 gas ratio is about 5:1. The dummy substrate is removed from the chamber after the process byproduct elimination process. And then, the ashing process is performed after inserting a second substrate into the chamber, wherein the second substrate has the photo resist pattern thereon to form the source and drain electrodes (step S43). At this moment, SF6 gas to O2 gas ratio used in the ashing process is about 1:20.
Because of the process gas, which is not removed and remains after the process byproduct elimination process, an ashing time is reduced in the photo resist pattern for which the ashing process is first performed after the process byproduct elimination process. Further, the dry etching process time of the protective film takes relatively longer and, at the same time, the temperature within the chamber is likely to increase because RF power is used during the dry etching process. In the case that the etching process and the ashing process are continuously performed, the rising temperature within the chamber increases generation of radicals during the ashing process that further shortens the ashing time. The ashing time of the long side or outer area of the substrate is especially reduced. The reduced ashing time causes the photo resist pattern to be ashed away excessively. If a lower part film located at the lower part of the photo resist pattern is patterned, there is a problem in that the lower part film is excessively etched.